Package Layout Engineer

Mountain View, CAfull timeOn Site

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mid

$157k–$176k

H1B: yes

Lightmatter Package Layout Engineer at Lightmatter delivers IC package substrate layouts supporting package architecture from concept through design optimization. The role involves collaboration with suppliers and adherence to signal integrity, power integrity, thermal, and mechanical requirements.

Responsibilities

Lightmatter is looking for a Package Layout Design Engineer to drive the next generation products from concept to development. You will be part of the Signal Integrity, Power Integrity and Packaging team, tasked with delivering substrate layouts that support the package architecture from concept, through design optimization and completion, meeting stringent signal integrity, power integrity, and design for manufacturing requirements. This position offers a unique opportunity to work on new package architectures by solving complex interactions across digital, analog and photonics domains.
Deliver IC package substrate layouts for standard and advanced packaging technologies.
Contribute to the product concept phase by delivering preliminary substrate designs and floorplanning to support overall stack-up (Silicon/package/MB) optimization.
Collaborate with package substrate suppliers and Outsourced Semiconductor Assembly and Test (OSAT) companies to apply layout design rules, stack up, and implementation guidelines.
Generate fab files and coordinate with substrate suppliers and OSATs to support Design for Manufacturing (DFM) and Design for Assembly (DFA) closure.
Design package layouts while adhering to signal integrity, power integrity, thermal, and mechanical requirements.
Design packages incorporating analog and digital elements/interfaces.
Support signal/power integrity engineers by providing iterative test routes to refine design rules and routing topologies.
Coordinate across functional teams to execute error-free Package Design Tape Outs on schedule.
Support and adapt design automation and verification activities to improve team efficiency.

Qualification

Proficient with Allegro X APDFamiliarity with layout tools (eExperience evaluating floorplans

Required

B.S. or M.S. degree in Electrical Engineering or similar discipline with at least 5 years of relevant experience
Minimum 3–5 years of experience in IC package layout design.
Proficient with Allegro X APD.
Understanding of IC package substrates and organic materials, and their impact on package design.

Preferred

Educational background in IC packaging and substrate layout design.
Familiarity with system-level validation tools such as Cadence Integrity 3DIC for package/IC codesign.
Familiarity with layout tools (e.g., Expedition Package Designer, Pads Layout, Altium, etc.).
Experience with layout tool scripting languages (e.g., SKILL or Python) to enable design automation.
Exposure to or interest in early-stage architectural pathfinding and physical feasibility studies for multi-chiplet and advanced packaging architectures (2.5D/3D IC, Silicon Interposers, EMIB, Fan-Out Chip-on-Wafer, etc.).
Experience evaluating floorplans, escape routing, bump patterns (micro-bumps / hybrid bonding), and die-to-die (D2D) interface topologies.
Excellent communication skills and the ability to collaborate effectively in cross-functional teams.