Signal Integrity Solutions Architect Intern

San JoseinternshipOn Site

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senior

$73k

H1B: yes

Astera Labs Signal Integrity Solutions Architect Intern models system-level channels for next-generation AI infrastructure to influence product roadmaps. Performs sensitivity and trade-off analyses and collaborates cross-functionally to align on signal integrity goals.

Responsibilities

System Channel Modeling
Build and run system-level channel models for a variety of compute and switch architectures
Evaluate the feasibility of next-generation architectures across PCIe, Ethernet, and UALink interconnects
Identify constraints, bottlenecks, and limitations in end-to-end channel performance
Sensitivity and Trade-off Analysis
Perform sensitivity analyses to understand interaction effects between channel parameters
Determine the main drivers of channel performance and quantify their impact on margin
Explore design trade-offs to define what is achievable at the system level
Roadmap and Cross-Functional Influence
Translate modeling results into system-driven inputs that shape product roadmaps and feature sets
Partner with solutions architecture, hardware engineering, and silicon engineering teams to align on signal integrity goals
Document findings and present results to technical teams and stakeholders in clear, concise formats

Qualification

Familiarity with PCIe Gen 6 or Gen 7Internship experience and compensationThis is a paidEqual opportunity

Required

Currently pursuing a Bachelor's degree in Electrical Engineering, Computer Engineering, Physics, or a related technical field
Coursework or project experience in signal integrity, transmission lines, electromagnetics, or high-speed digital design
Basic understanding of high-speed serial link concepts such as insertion loss, return loss, crosstalk, and equalization
Familiarity with the physical layer of high-speed interconnect standards such as PCIe or Ethernet
Proficiency with a scripting or analysis tool such as Python or MATLAB for data processing and modeling
Strong written and verbal communication skills, with the ability to present technical findings clearly

Preferred

Currently pursuing a Master's or PhD in Electrical Engineering or a related field
Hands-on experience with channel simulation tools (e.g., Keysight ADS, Ansys HFSS, or similar) or S-parameter analysis
Familiarity with PCIe Gen 6 or Gen 7, high-speed Ethernet, or UALink
Experience with statistical or design-of-experiments methods for sensitivity analysis
Curiosity and initiative to learn quickly in a fast-paced, collaborative environment
Internship experience and compensation
This is a paid, hourly U.S. internship. The applicable hourly rate is determined as part of the offer process and specified in the offer letter, depending on education level ranges from $35/hour to $55/hour. U.S. interns currently receive a $500-per-week housing/relocation stipend for the duration of the internship. Interns participate in Early Career programming, including technical and professional-development sessions, community events, and an end-of-program project presentation.
Equal opportunity