We're looking for a low-level embedded software engineer who will own the core firmware and embedded software foundation of Era-Node, our flight autonomy module. You will be responsible for taking the embedded architecture from a blank sheet of paper all the way into orbit. This means writing the device drivers, custom RTOS/bare-metal code, and deterministic state machines that interface our star trackers and compute systems with the host spacecraft.
This is a 0->1 role. You will define the firmware architecture, write the low-level hardware interfaces, and implement the logic that orchestrates microsecond-level sensor timing and serial communications. Crucially, you will bridge the gap between hardware and high-level autonomy by optimizing low-level compute pipelines, ensuring our onboard AI and GNC (Guidance, Navigation, and Control) algorithms run with maximum efficiency and minimal latency. You will work closely with the payload hardware and autonomy teams to ensure the software layer flawlessly manages hardware resources in the harsh, radiation-prone environment of space.
Own the end-to-end embedded software architecture for Era-Node, developing highly reliable bare-metal and RTOS-based firmware in C/C++.
Optimize low-level compute pipelines, memory access patterns (e.g., DMA), and hardware accelerators to maximize performance and execution speed for onboard GNC algorithms and AI/ML computer vision models.
Write and optimize low-level hardware drivers for image sensors, compute modules, memory devices, and spacecraft interfaces.
Develop deterministic state machines and low-level logic to handle precise timing systems, interrupt routines, and hardware synchronization across multiple optical sensors and compute nodes.
Implement, debug, and optimize robust serial communications software stacks spanning inter-board and spacecraft-to-payload links (e.g., RS-422, SpaceWire, CAN, SPI, I2C, UART).
Implement software-level fault tolerance and radiation mitigation strategies, such as watchdog timers, memory scrubbing, and error handling for Single Event Upset (SEU) bit flips.
Lead board bring-up for custom hardware, using debuggers (JTAG/SWD), oscilloscopes, and logic analyzers to verify hardware-software integration and timing constraints.
Architect and implement microsecond-precise software timing and hardware triggering systems to flawlessly synchronize data capture between flight cameras and motion hardware on our robotic lab testbeds.
Develop hardware-in-the-loop (HIL) test platforms that integrate flight computers, sensors, cameras.
Support environmental test campaigns (thermal vacuum, vibration) by writing automated test scripts and diagnostic firmware to validate hardware health during stress testing.
