K2 Space Photonic IC Design Engineer at K2 Space responsible for designing photonic integrated circuits and packages for satellite payloads. Own the chip-to-system boundary optically and electrically, ensuring ruggedness for space deployment.
Responsibilities
K2's ambitions extend beyond the satellite bus. By designing and operating our own spacecraft and regularly manifesting hardware to orbit, K2 is uniquely positioned to develop, test, and deploy ambitious, “limit-of-physics” optical and photonic payloads across MEO, GEO, cislunar, and deep space on unprecedented timelines. The satellite bus is the platform – the payloads are the mission.
As a Photonic IC Design Engineer focused on chip-to-system integration, you will design photonic integrated circuits (PICs) and the packages that connect them to the outside world: small, light, low-cost, and rugged enough to fly at constellation scale. You will own the boundary between chip and system on both sides: optically, how light gets on and off the chip and how fibers are attached and held; electrically, the high-speed modulators, RF interfaces, and bias and tuning control that connect the PIC to its drive electronics. You will also make sure the whole assembly survives launch and years in orbit. Your coupling-loss, modulator, and bandwidth numbers feed directly into system link budgets, so you will work closely with K2's systems, photonics test and automation, RF, ASIC, and manufacturing teams, and with external foundry and packaging partners. As a founding member of the photonics team, you will help set how K2 designs, packages, and qualifies photonic hardware.
Design, simulate, and lay out PIC devices and circuits (edge and grating couplers, spot-size converters, photodetectors, and passive components) from specification to tapeout on commercial integrated photonics foundry platforms.
Design high-speed modulators (e.g., traveling-wave Mach-Zehnder and ring modulators), including electrodes, terminations, and RF launches, and co-design them with RF and ASIC engineers against driver and TIA specifications.
Implement bias and tuning control in hardware: place heaters and monitor photodiodes, define the drive and readout interface with K2's electronics engineers, and bring up closed-loop modulator bias and resonator locking, verified over temperature and radiation.
Set the optical I/O requirements (coupling loss, alignment tolerance, polarization, and I/O placement on the die) and work them into the floorplan with chip designers and into the link budget with systems engineers.
Design the mechanical side of the package in 3D CAD: PIC carriers and submounts, fiber-array V-groove and lid geometry, strain relief, and alignment and assembly fixtures, with tolerance stack-ups tied back to the coupling-loss budget.
Drive radiation, thermal-vacuum, and vibration qualification of photonic devices and packages: write the test plans, lead the campaigns alongside K2's test and reliability engineers and outside test facilities, and turn the results into design rules.
Partner with the photonics test and automation team on characterization: define test plans and pass/fail metrics, design test structures and probe- and fiber-array-compatible layouts, help bring up and validate automated measurements, and use the shared data pipeline to close the loop between simulation, measurement, and design.
Carry the high-speed electrical path through the package (wirebond or flip-chip transitions and RF interconnects to the drive electronics) and present designs at preliminary and critical design reviews.
Qualification
PhD or MS in electrical engineeringHands-on work at the chip boundaryPhotonic device simulation (Meep3D mechanical CAD (eRadiationModulator bias control
Required
PhD or MS in electrical engineering, optics, physics, or a related field, or a Bachelor's degree with equivalent experience.
PIC designs taken through tapeout on one or more commercial integrated photonics platforms (e.g., silicon photonics, silicon nitride, indium phosphide, thin-film lithium niobate), with the fabricated devices characterized in the lab.
Hands-on work at the chip boundary: optical I/O design with fiber attach or packaging, or high-speed modulator and RF design measured with a VNA (S-parameters, electro-optic bandwidth).
Photonic device simulation (Meep, Tidy3D, Lumerical FDTD, FEM, or EME), layout tools (e.g., KLayout, gdsfactory, Cadence), and Python for automation and data analysis.
Preferred
3D mechanical CAD (e.g., SolidWorks, Inventor, Fusion) for package parts or fixtures, including drawings that a machine shop can build from.
Radiation, thermal-vacuum, or vibration testing of photonic or electronic devices.
Inverse design or topology optimization of couplers and other optical I/O devices.
RF package or board design to tens of GHz (e.g., HFSS, Sonnet).
Heterogeneous or 3D integration and co-packaged optics.
Hardware built for space or other harsh environments.
Modulator bias control, resonator locking, or other closed-loop control of photonic devices.
