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VelauraPosted Sep 15, 2026
SoC Design Verification Engineer
Santa Clara, CAfull timeOn Site$200k–$300kH1B: no
Velaura SoC Design Verification Engineer at Velaura to lead system level verification of next generation Physical AI SoC. Responsible for owning the SoC verification plan through sign off and tape out.
Responsibilities
- We are looking for an experienced verification leader to help verify and deliver Velaura's next generation Physical AI SoC. You will work closely with architects, RTL engineers, software engineers and system teams to establish confidence in the correctness, performance, reliability and safety of the design, from individual RTL blocks through complete hardware and software systems running real workloads.
- This role leads system level verification. You will own the SoC verification plan and carry it through sign off and into tape out, covering boot and root of trust, clock and reset topology, low power behavior, and the IO and memory subsystems. You will set technical direction for a small team while staying hands on in the environment yourself.
Company
Velaura
View company pageSource: lever
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