AMS Verification Engineer (RFIC Engineering)

Preferred

• Master’s degree or PhD in an engineering discipline with emphasis in integrated circuit design/verification
• Experience with AMS simulation tools and flows
• Experience with annotated gate-level simulation within an AMS simulator
• Experience in System-Verilog, UVM, Python
• Experience in writing behavioral models for analog/mixed-mode IPs in Verilog-A/AMS
• Understanding of analog circuit fundamentals, and experience simulating circuits such as LDOs, bandgaps, DACs, ADCs, baseband amplifiers, mixers, RF amplifiers, oscillators, PLLs, etc.
• Understanding of combinational logic and basic digital circuit blocks, such as flip-flops, counters, buffers, synchronizers, serializers/de-serializers, etc.; ability to understand RTL and gate-level netlists
• ADDITIONAL REQUIREMENTS: