Senior ASIC Design Verification Engineer

Seattlefull timeOn Site

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senior

$170k–$250k

H1B: no

K2 Space Senior ASIC Design Verification Engineer responsible for verifying functionality, performance, and robustness of custom silicon designs. Leads verification approach and collaborates with multiple engineering teams to ensure comprehensive test coverage.

Responsibilities

We are seeking a Principal ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon.
Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.
Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.
Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
Participate in ASIC team interviews.

Qualification

Solid understanding of SystemVerilogExperience with test planningExperience with regression managementExperience with low power verificationFamiliarity with physical design flowsExperience working in cross-functionalExperience in space

Required

B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
10+ years of experience in ASIC/SoC verification.
Solid understanding of SystemVerilog, digital logic, RTL design, DFT, and hardware design and verification flows.
Proficiency with several simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tools, and scripting languages (ex: Python, Perl, TCL).
Experience with test planning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
Experience with regression management, coverage analysis, revision control (ex: Git), CI/CD automation, and gate-level simulation.
Experience with developing and integrating reference models.
Experience with embedded processor-based designs and firmware/bare metal coding (ex: C, C++).
Understanding of many industry-standard interfaces (ex: APB/AHB/AXI).
Involvement in post-silicon validation planning and execution.