SpaceX Sr. SOC Physical Verification Engineer at SpaceX responsible for full-chip physical verification and flow development for advanced node SoCs. Works cross-functionally to ensure tapeout readiness and leverages AI for automation.
Responsibilities
Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools like Calibre, ICV, or Pegasus
Develop, maintain, and optimize physical verification flows for advanced node SoC’s.
Interpret and implement foundry Design Rule Manuals (DRM) — translate rule updates into verified flow changes
Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs
Perform ESD verification — validate protection strategies, current paths, and CDM/HBM compliance
Drive tapeout readiness by coordinating signoff across block and top-level and Hard IP design teams
Engage directly with foundry teams to resolve DRM ambiguities and waiver requests.
Develop/modify design flows as needed to meet the overall design quality of results and chip integration requirements.Leverage AI agents to automate rule deck validation, violation triage, and signoff reporting workflows
Qualification
Experience in IP integration (eDeep expertise in DRCHands-on proficiency with CalibreExcellent scripting skills (csh/bash
Required
Bachelor’s degree in electrical engineering, computer engineering or computer science
5+ years of ASIC and/or physical design flow development experience in industry
Preferred
Experience and deep understanding of SOC top level physical design flows (floor-planning, I/O, bump & RDL planning, hard IP integration, partitioning, power/ground grid generation, pin assignment, DFT, partition hardening, special clock handling, feedthrough flows, special interface/interconnect planning and implementation)
Experience in IP integration (e.g. memories, I/O’s, analog IPs, SerDes, DDR etc.)
Deep expertise in DRC, LVS, PERC and ESD verification methodologies
Hands-on proficiency with Calibre, ICV (IC Validator), or Pegasus
Direct foundry DRM experience — able to read, interpret, and implement complex rule decks
Experience at advanced nodes (4nm and below)
Experience with large SOC designs (>10M gates) with frequencies in excess of 1GHZ
