Signal/Power Integrity Hardware Engineer

San Josefull time

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senior

$110k

H1B: no

Skhynixmemorysolutionsamericainc Senior Signal Integrity Engineer role focused on developing next generation SSD products with expertise in hardware design and signal/power integrity. The position involves mentoring engineers and providing SI/PI expertise for SSD controller package and PCB design.

Responsibilities

Mentoring of engineers.
Provide SI/PI expertise for SSD controller package (SoC) substrate design and SSD PCB design.
Participate in the design of SSD products which includes: design guidelines, reviewing designs, validation of designs and final reports of work designs.
Support PCB back-end process: defining stack-up and HDI via technologies, part placement, setting routing constraints and reviews.
Interface with cross functional teams to ensure the design meets all system level requirements through verification/validation in the lab.
Work closely with SoC, FW, package, and circuit design engineers.
Documentation and communication to design, product and executive teams.
Debug and root cause analysis at all product development stages, as well as customer escalations.

Qualification

BS in Electrical Engineering requiredHigh-speed SSD board designsRequired experience of EM field solversTechnical leader experienceFamiliar with PCISIG

Required

BS in Electrical Engineering required; MS in Electrical Engineering is a plus.
3-8+ years of relevant working experience.
High-speed SSD board designs, pre layout simulation, post layout simulation and design layout guide generation for PCIe Gen4/5/6, DDR4/5, LPDDR4/4x, NVIO and PDN.
Strong fundamentals in 3D/2D EM simulation tools and transmission line theory.
Required experience of EM field solvers, time and frequency domain simulation tools like Sigrity, Allegro, ADS, HFSS, SIWAVE, and HSPICE.
Simulation followed by measurement correlation using Oscilloscope, VNA and TDR equipment.
Excellent understanding of PCB design fundamentals: single end and differential signaling, cross talk (near end and far end), signal loss and impedance control.
Excellent written and verbal communication.

Preferred

Technical leader experience.
Familiar with generating and interpreting data & eye diagrams at PCIe GENx speeds: NRZ, PAM3, PAM4, PAMx.
High Frequency pcb low loss board material experience.
Experience with flex circuit design for high speed signaling.
Familiarity with PCIe operation and DRAM operation for optimizing driver and receiver equalization schemes.
Knowledge of IBIS and ability to take common simulation outputs such as S-parameters from various components and determine at the system level that PRD requirements are met.
Optimizing PDN and extracting PDN for PSIJ Analysis.
Familiar with PCISIG, JEDEC and ONFI specifications and compliance.

Benefits

Dental
Vision
401(k)
Equity/RSU
Life Insurance

Company

Skhynixmemorysolutionsamericainc

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Source: greenhouse

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