Synthesis & STA Engineer – High-Speed SerDes at Astera Labs · LumiJobs

Responsibilities

Perform RTL synthesis, driving area, power, and timing optimization for digital controller and DSP blocks within high-speed SerDes PHY designs.
Author, develop, and validate SDC constraints from scratch, including clock definitions, generated clocks, multi-frequency/multi-mode constraints, I/O delays, false paths, multicycle paths, and clock-domain crossing exceptions unique to SerDes architectures.
Set up and manage MMMC (Multi-Mode Multi-Corner) environments to enable accurate and efficient STA across process, voltage, and temperature (PVT) corners.
Drive timing closure from synthesis through sign-off, ensuring robust timing across digital blocks embedded within analog/mixed-signal SerDes IP and full-chip SoC integration.
Define and manage I/O timing budgets and interface constraints between analog and digital boundaries in hierarchical mixed-signal designs.
Apply advanced sign-off methodologies at TSMC 5nm/3nm and below, including OCV/AOCV/POCV and PVT effects relevant to high-speed serial link performance.
Leverage ETM/ILM libraries for hierarchical timing analysis and correlation of SerDes hard-macro blocks, balancing runtime and accuracy.
Provide actionable timing feedback at both block and full-chip levels, including root cause analysis, timing debug, and ECO guidance for SerDes digital logic.
Manage large-scale multi-corner/multi-mode STA runs with automation, partitioning, and efficient resource usage, developing scripts and flows to improve turnaround time.
Generate and validate timing ECOs, partnering with physical design, analog, and RTL teams for quick closure on high-speed data-path and clock-path issues.
Partner closely with analog/mixed-signal designers, SerDes architecture, implementation, and verification teams to drive timing convergence and provide sign-off level expertise for PHY-level and chip-level integration.
Collaborate on clock tree and power domain strategies for SerDes digital blocks, ensuring compatibility with PLL/CDR-generated clocks and multi-supply domains.

Synthesis & STA Engineer – High-Speed SerDes

Responsibilities

Qualification

Required

Preferred

Benefits

Company

Astera Labs

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