Principal Design Verification Engineer- SerDes/PHY IP

San Josefull timeOn Site

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senior

$207k–$230k

H1B: yes

Astera Labs Principal Design Verification Engineer at Astera Labs owns functional verification of high-speed SerDes/PHY IP for AI infrastructure. The role includes architecting verification environments and ensuring first-pass silicon success.

Responsibilities

Astera Labs is hiring a Principal Design Verification Engineer to own functional verification of our high-speed SerDes/PHY IP — the connectivity engine powering rack-scale AI infrastructure. You will architect verification environments, drive coverage closure, and ensure first-pass silicon success on the analog/digital boundary that defines next-generation AI systems.
This is a high-impact, hands-on role at the heart of Astera Labs' hyper-growth story. You'll partner directly with PHY analog/mixed-signal designers, digital architects, and SoC integration teams to verify multi-Gbps SerDes blocks that ship into the world's most advanced AI platforms, including UALink, UCIe, PCIe Gen 6/Gen 7, and Ethernet-based connectivity products.
Verification Architecture & Strategy
Architect UVM-based verification environments for SerDes/PHY IP, including PMA, PCS, and PHY-MAC interface layers
Define verification plans, coverage models, and sign-off criteria for high-speed serial link blocks
Drive methodology decisions across analog/mixed-signal co-simulation, gate-level simulation, and emulation flows
Execution & Coverage Closure
Develop SystemVerilog/UVM testbenches, sequences, scoreboards, and reference models for multi-Gbps SerDes lanes
Execute functional, performance, and corner-case verification across equalization, CDR, training, and link bring-up scenarios
Lead coverage analysis and closure, debug failures with designers, and drive regressions to clean tape-out
Physical Layer & Protocol Verification
Verify PHY behavior against industry specifications including PCIe Gen 6/Gen 7, UALink, UCIe, and Ethernet PHY standards

Qualification

Experience verifying PCIe Gen 6/Gen 7Salary range is $207

Required

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
8+ years of design verification experience on high-speed SerDes, PHY, or mixed-signal IP
Strong understanding of the physical layer, including equalization (CTLE, DFE, FFE), CDR, training sequences, and link bring-up
Expert-level proficiency in SystemVerilog and UVM
Hands-on experience with analog/mixed-signal co-simulation and Real Number Modeling (RNM)
Working knowledge of one or more high-speed serial protocols: PCIe, UALink, UCIe, Ethernet, or CXL

Preferred

MS or PhD in Electrical Engineering or Computer Engineering
Experience verifying PCIe Gen 6/Gen 7, UALink, or UCIe SerDes/PHY IP
Familiarity with emulation platforms (Palladium, Veloce, or ZeBu) and gate-level simulation flows
Scripting proficiency in Python or Perl for verification automation and regression management
Experience supporting post-silicon bring-up and correlating pre-silicon coverage with silicon results
Proven ability to lead technically across a multi-disciplinary team in a fast-paced environment
Salary range is $207,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Company

Astera Labs

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Source: greenhouse

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Principal Design Verification Engineer- SerDes/PHY IP at Astera Labs · LumiJobs