Terac This role involves participating in a paid study on RTL implementation and hardware description workflows. The engineer will review RTL scenarios and discuss automated evaluation and verification challenges.

Responsibilities

We are looking for experienced hardware engineers who specialize in RTL design and implementation. We welcome ASIC designers, FPGA engineers, hardware verification specialists, and system-on-chip (SoC) architects. You should have hands-on experience with hardware description languages and automated evaluation frameworks.
Walk us through your approach to RTL implementation and hardware description
Review and react to specific automated evaluation scenarios
Describe a recent time you tackled a complex hardware verification challenge
Provide feedback on current workflows and tooling gaps
Who Should Apply
Professional experience in hardware engineering or RTL design
Hands-on background with hardware description languages (Verilog, VHDL, or SystemVerilog)
Familiarity with automated evaluation and verification workflows
Comfortable discussing technical design choices in a remote interview

Qualification

Required

Professional experience in hardware engineering or RTL design
Hands-on background with hardware description languages (Verilog, VHDL, or SystemVerilog)
Familiarity with automated evaluation and verification workflows
Comfortable discussing technical design choices in a remote interview