Senior / Staff Engineer – SerDes Analog/Mixed-Signal Design

Preferred

• Experience developing high-speed SerDes, wireline transceivers, data converters, clocking circuits, or other analog/mixed-signal IP.
• Experience developing AI-driven schematic or layout workflows.
• Familiarity with advanced CMOS process technologies and their circuit-design challenges.
• Experience with post-layout simulation, parasitic extraction, and circuit-performance optimization.
• Exposure to silicon bring-up, characterization, and circuit debug.
• Ability to independently own design tasks and drive them to completion.
• Experience in one or more of the following technical areas:
• Fractional-N PLL, LC-VCO, DTC/TDC, multi-modulus divider (MMD).