Senior Engineer, Serdes Analog Design

SSI San Jose full timeOn Site

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senior

$138k–$206k

H1B: yes

Samsung Semiconductor Senior Engineer, Serdes Analog Design at Samsung Semiconductor designs high-speed interconnect transceiver circuits including Serdes IPs and clock generation. The role involves developing low-power, low-voltage analog and custom digital circuit components using advanced CMOS technologies.

Responsibilities

You’ll work with a team to develop high-performance and low-power serdes, including display interface, camera sensor interface, UCIe / die-to-die interconnect and 224/448Gbps UA-link/Ethernet using cutting-edge process technologies.
Location: Daily onsite presence at our San Jose, CA headquarters in alignment with our Flexible Work policy
Design low-power and low-voltage analog and custom digital circuit components using advanced CMOS process technologies
Translate component design specification to schematics. Build simulation test-benches to evaluate circuit performance, functionality, power consumption and reliability.
Supervise layout designers to generate LVS/DRC clean layout. Optimize layout to improve the power consumption and performance of circuits
Functionality and performance validation in Silicon
Bachelors with 5+ years, Masters with 3+ years or PhDs with 0+ years of experience.
Minimum 2+ yrs experience RF/Analog/Serdes SoC design experience.
Knowledge and experience with analog circuits/mixed signal circuits: such as bandgap, LDO, filters.
Knowledge and experience with circuits of Serdes IPS: CTLE, DFE, FFE, clock distributions, PI, IQ generation.
Knowledge of Serdes architecture and high-speed interconnect standard (USB, PCIe, UCIe)
Knowledge and experience with ESD, PLL, clock generation, ADC, DAC is a big plus.