Principal PCS/PMA RTL Design Engineer at Astera Labs · LumiJobs

Qualification

Master's degree is preferredExperience with RTL simulationDirect experience designing PCSExperience with PAM4 signalingFamiliarity with the PIPE specificationExperience with multi-laneFamiliarity with interconnectFamiliarity with lint

Required

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
Master's degree is preferred.
3+ years of relevant experience in digital ASIC, SoC, or RTL design, or equivalent academic and industry experience.
Hands-on experience with Verilog or SystemVerilog RTL development.
Understanding of digital design fundamentals, including combinational and sequential logic, clocks, resets, state machines, datapaths, FIFOs, and interfaces.
Working knowledge of at least one high-speed serial protocol (Ethernet, PCIe, UCIe, UALink, CXL, or similar) at the PCS/PHY layer.
Experience with RTL simulation, debugging, synthesis, and basic timing analysis.
Familiarity with ASIC design flows and collaboration across design and verification teams.
Strong communication skills and the ability to work effectively in a collaborative, fast-paced environment.
Ability and willingness to work onsite in San Jose, California.

Preferred

Direct experience designing PCS, PMA, or PHY digital logic for Ethernet (25G–224G per lane, 100G/200G/400G/800G/1.6T), PCIe (Gen4/5/6/7), UCIe, UALink, CXL, or similar standards.
Experience with PAM4 signaling, FEC (RS-FEC/KP4, FLIT-mode FEC/CRC), lane deskew/alignment, link training, and equalization control.
Familiarity with the PIPE specification, 802.3 Clause 73/72/136/162-series, PCIe LTSSM, and UCIe link training and sideband.
Experience with multi-lane, multi-rate SerDes digital datapaths and clocking architectures.
Familiarity with interconnect, networking, or data-center ASICs (retimers, switches, NICs, DPUs, SmartNICs, NoCs).
Familiarity with synthesis and implementation tools such as Cadence Genus/Innovus or Synopsys Design Compiler/ICC2.
Experience with STA using tools such as Synopsys PrimeTime or Cadence Tempus.
Familiarity with lint, CDC/RDC, DFT, scan, GLS, LEC, UPF, or formal-verification flows.

Principal PCS/PMA RTL Design Engineer

Responsibilities

Qualification

Required

Preferred

Company

Astera Labs

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