SpaceX Sr. ASIC Design Engineer at SpaceX responsible for physical design and implementation of next-generation silicon for Starlink. Collaborates with cross-disciplinary teams to develop and optimize ASIC design flows.
Responsibilities
Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
Develop/improve physical design methodologies and automation scripts for various implementation steps
Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop
Qualification
Good scripting skills (csh/bash
Required
Bachelor’s degree in electrical engineering, computer engineering or computer science
5+ years of ASIC and/or physical design flow development experience in industry
Preferred
Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows
Strong experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms
Knowledge of deep sub-micron FinFET and CMOS solid state physics
Knowledge of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
Familiar with CMOS analog circuit and physical design
Knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows
Good scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
