Sr. ASIC DFT Engineer (Silicon)

Austin, TXfull timeOn Site

Apply on Employer Site

senior

$175k–$280k

H1B: no

SpaceX Sr. ASIC DFT Engineer at SpaceX develops next-generation ASICs for space and ground infrastructure, focusing on Design for Test (DFT) implementation and optimization. The role involves working with cross-disciplinary teams and leveraging Siemens Tessent tools for DFT architectures.

Responsibilities

Implement and optimize DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools
Integration and verification of Design for Test (DFT) IPs and fabrics within Subsystems
Set up and run Automatic Test Pattern Generation (ATPG) tools and methodologies, including generating patterns for stuck-at, transition, and path delay fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows.
Run and debug non-timing and SDF annotated gate-level simulations
Create and validate DFT patterns for post-silicon bringup and also help with ATE debug through all cycles of silicon characterization
Develop test scripts, automate processes, and analyze data using programming languages such as Perl, Python, Tcl, or C++

Qualification

Experience with In-System Test (IST)

Required

Bachelor’s degree in electrical engineering, computer engineering, or physics
5+ years of experience in semiconductor Design For Test (DFT) engineering, post-silicon validation, and/or production testing

Preferred

Master’s or PhD in electrical engineering, computer engineering, physics, or related engineering field
Extensive experience in post-silicon bringup, including silicon debug, failure analysis, and yield optimization on complex SoCs or ASICs
Hands-on experience with Automated Test Equipment (ATE) platforms (e.g., Teradyne, Advantest) for high-volume manufacturing test development and debug
Experience collaborating with cross-functional teams (e.g., design, verification, and manufacturing) to ensure DFT features meet production requirements, utilizing Siemens Tessent workflows
Knowledge of industry standards for testability (e.g., IEEE 1500, 1687) and experience with low-power DFT techniques using Siemens Tessent
Experience with In-System Test (IST), boundary scan (IEEE 1149.1), functional testing in embedded systems, or board-level diagnostics, preferably using Siemens Tessent tools
Hands-on experience with Tessent Streaming Scan Network
Experience with cell-aware fault models in ATPG

Benefits

Dental
Vision
401(k)
Parental Leave
Life Insurance

Company

SpaceX

View company page

Source: greenhouse

Active within the past hour

More roles at SpaceX

Supervisor, Quality Assurance (Starlink Aviation)

Woodinville, WA

Sr. Sourcing Specialist, PCB/PCBA (Starshield)

Hawthorne, CA

Sr. Software Engineer, Full Stack (Data & Video Analysis)

Hawthorne, CA

Sr. Wireless Software Engineer (Starlink)

Palo Alto, CA