Own the ASIC methodology and end-to-end delivery of ambitious AI compute silicons, from microarchitecture and RTL through verification, physical design, signoff, and tapeout. Build a fundamentally faster, AI-native chip-development flow, using automation, intelligent agents, and data-driven feedback loops to accelerate design iteration, verification, closure, and engineering productivity. Lead a world-class team, set an uncompromising bar for PPA and silicon quality, and personally drive the most consequential technical and execution decisions.

What We'd Like to See

Repeated tapeout success: Direct leadership of multiple complex, production-volume ASIC or SoC programs, ideally at advanced process nodes.

End-to-end ASIC mastery: Deep expertise spanning RTL, functional verification, synthesis, timing closure, physical implementation, DFT, signoff, and silicon bring-up.

Methodology innovator: A track record of transforming design flows through automation, ML/AI-assisted EDA, verification productivity, or scalable engineering infrastructure—not merely operating established processes.

Execution excellence: A demonstrated ability to deliver demanding programs with strong first-silicon outcomes and disciplined engineering tradeoffs.

Elite team builder: A record of recruiting, developing, and leading world-class silicon engineers and technical leaders.

Hands-on leadership: Credibility to resolve difficult cross-functional engineering problems personally while building processes that scale.

Vice President of ASIC Engineering

Responsibilities

Qualification

Required

Benefits

Company

Architect

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