Drive CPU verification strategy, develop test plans for functional blocks based on specifications targeting micro-architectural & ISA features,

Architect, build and maintain SystemVerilog/C++ based testbench components, including stimulus generators, checkers, scoreboards, monitors, and reference models

Develop directed and pseudo-random tests from Random Instruction Generators to verify CPU functionality and stress corner cases

Define, implement, and close functional and code coverage goals, analyzing holes and driving them to closure

Debug & root-cause failures across RTL, testbench, and reference models, and work with RTL designers to root-cause and resolve bugs

Partner cross-functionally with RTL design, performance modeling, CAD/methodology, and software teams to align on verification strategy, improve tools and flows, and drive shared quality, schedule, and tape-out goals.

Apply formal verification, assertions (SVA), and emulation where appropriate to improve verification quality and efficiency

Run and maintain regressions across various platforms including Simulation, Emulation, FPGA’s and track bug trends and verification progress metrics

Participate in microarchitecture, RTL, and verification reviews and write technical documentation

CPU Design Verification Engineer - Full Time

Responsibilities

Qualification

Required

Company

Rosaic Labs

More roles at Rosaic Labs