Design Verification Intern -RISCV CPU

Required

• Passionate about computer architecture and curious about how cutting-edge CPUs actually work.
• Enrolled in a BS, MS, or PhD program in EE, CE, CS, or a related field, with a strong academic record.
• Experienced with C++, SystemVerilog, or scripting languages through coursework or personal projects.
• Comfortable thinking at both the software and hardware level—including assembly and RTL.
• Contribute to the functional verification of high-performance CPUs designed for general purpose and AI/ML applications.
• Help develop DV test plans and testbenches for both ISA and microarchitecture-level features.
• Debug RTL code and assist in making real design changes that impact chip development.
• Build tools and write stimulus code that can scale across pre-silicon to post-silicon environments.
• What You Will Learn
• Get hands-on experience verifying state-of-the-art AI/ML hardware with guidance from experienced engineers.
• Explore how performance, RTL, and DV tools come together in a full-chip environment.
• Deepen your understanding of CPU design, ISA-level verification, and system-level debugging.