Staff Engineer, Physical Design

Required

• Experienced with synthesis and place-and-route flows, especially using Synopsys Design Compiler / Fusion Compiler and IC Compiler II.
• Comfortable in a small, cross-functional physical design team, owning a block or subsystem and partnering on tapeout milestones with clear communication and accountability.
• Ideally bring extra depth in areas such as UPF/multi-voltage power domains, SoC interface IP integration (e.g. I3C, UART), signoff breadth (DRC/LVS, EM/IR, LEC/Formality), multi-clock/CDC-aware implementation, PLL/DLL integration, and DFT-aware physical implementation (OCC/MBIST).
• Execute synthesis, PNR, and STA for assigned partitions of a complex AI SoC.
• Help close EM/IR, ensure UPF power intent is consistent with implementation, and drive LEC and physical verification signoff for your partitions in coordination with methodology owners.
• Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.
• What you will learn
• How to implement and close AI SoC partitions end-to-end, including power intent, timing, and physical signoff in a modern Synopsys-based flow.
• Deeper expertise across signoff domains: EM/IR, DRC/LVS, logical equivalence (LEC/Formality), and CDC-aware implementation on meaningful production blocks.
• Practical integration of analog/mixed-signal macros (PLL/DLL), DFT features (OCC/MBIST), and SoC interface IP within advanced physical design flows and collaborative tapeout environments.