SpaceX Design Verification Engineer developing ASICs and FPGAs for Starlink projects using Verilog/SystemVerilog. Participates in full design lifecycle and collaborates with cross-functional teams.
Responsibilities
Design ASICs and/or FPGAs for Starlink projects, implementing IP for complex SoCs and participate in integration tasks using Verilog/SystemVerilog
Participate in the full ASIC/FPGA design lifecycle for Starlink projects, from high-level conceptual and architectural discussions through microarchitecture, design partitioning, and collaboration with backend/implementation teams, and assist in lab bring-up and validation
Engage in high-level architectural design for FPGA and ASICs
Collaborate with cross-functional engineers in developing new technologies for the Starlink program impacting User terminals, Satellites, and more
Qualification
ASIC/FPGA system integration experienceProficiency in Python for scripting
Required
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics
1+ years of experience in RTL Design using SystemVerilog, Verilog or VHDL
Preferred
Master’s in Electrical/Computer Engineering or related field
ASIC/FPGA system integration experience
Proficiency in Python for scripting
Experience in designing DSP or digital communication system datapath blocks
Experience with EDA tools such as HDL simulators
Experience and understanding of AXI/AHB/APB protocols
Strong foundation in electrical engineering fundamentals
Ability to work in a dynamic environment with changing needs and requirements
