Senior FPGA Verification Engineer, Air Dominance and Strike

Costa Mesa, CA (OC-00)full time

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On Site

senior

$166k–$220k

H1B: no

Anduril Industries Senior FPGA Verification Engineer responsible for verification of FPGA/SoC designs on AMD (Xilinx) platforms using UVM-based methodology. Focus on coverage-driven verification and compliance with DO-254 and safety standards.

Responsibilities

Architect and implement UVM verification environments (drivers, monitors, predictors, scoreboards) for AMD (Xilinx) FPGA/SoC designs
Develop verification plans with traceability to system and hardware requirements
Author SystemVerilog Assertions (SVA) for protocol compliance and design intent checks
Build functional coverage models and drive code coverage analysis to closure
Develop constrained-random and transaction-level test sequences to maximize coverage and uncover corner-case bugs
Establish and maintain regression suites, tracking coverage metrics and verification progress
Debug failures using waveform tools and simulation logs at the HDL and system level
Collaborate with design engineers on RTL reviews, bug resolution, and micro-architecture refinement
Support hardware validation and board bring-up on target platforms
Ensure verification meets DO-254 and relevant safety standards
Author verification closure reports and coverage analysis summaries

Qualification

Proficient in SystemVerilogObject-oriented programming principlesIndustry simulators (QuestaLinux development environmentsEligible to obtain and hold a UDO-254Digital interfacesSoC and ARM-based embedded platforms

Required

Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field
8+ years of experience in FPGA/ASIC verification
Proficient in SystemVerilog, UVM methodology and SVA, with experience contributing to and extending UVM testbenches
Object-oriented programming principles
Industry simulators (Questa, VCS, Xcelium, or Vivado)
Git-based collaborative workflows including code review
Linux development environments
Strong communication and teamwork skills
Eligible to obtain and hold a U.S. Secret security clearance

Preferred

12+ years of experience in FPGA/ASIC verification
Master’s degree in Electrical Engineering, Computer Engineering, or related field
DO-254, avionics verification standards for UAS, and safety-critical verification processes
SVUnit or equivalent unit-testing frameworks
Formal verification or CDC verification tools
Digital interfaces: Ethernet, PCIe, JESD204C, MIL-STD-1553, SPI
Verification automation scripting (Python, Tcl, Makefile)
SoC and ARM-based embedded platforms

Benefits

Vision
Equity/RSU

Company

Anduril Industries

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Source: greenhouse

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