Senior FPGA Engineer, EW

Costa Mesa, CA (OC-00)full timeOn Site

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senior

$166k–$220k

H1B: no

Anduril Industries Senior FPGA Engineer responsible for end-to-end design and verification on AMD/Xilinx SOC/FPGA platforms. Lead FPGA development for software defined radio platforms enabling electronic warfare functions.

Responsibilities

Own FPGA development for various software defined radio platforms that enable EW functions
Work with software, and electrical, engineers to bring up state of the art boards for software defined radios
Responsible for design and test of VHDL DSP modules and infrastructure
Integrate subsystem/module into larger FPGA core; solve resource and timing contentions as they arrive
Develop drivers for custom RF component boards (PLLs, mixed signal front ends, etc)
Manage project deliverables against timeline; effectively document and communicate

Qualification

8+ years professional experienceExperience with Xilinx/AMD SOC/FPGAsYou are a self starter$166

Required

8+ years professional experience
Strong experience with DSP implementation for embedded devices and/or software defined radios
Experience with Xilinx/AMD SOC/FPGAs; knowledgable of architecture
Experience with bring-up of high speed digital interfaces (PCIE, JESD, Aurora, N-Gbps Optical, etc)
Proficient in HDL design using VHDL and/or Verilog
Proficiency in a Linux development environment
Proficiency using Git and CI/CD workflows (Git, TCL, CI/HITL)
Experience mentoring/leading 1-3 engineers through larger design tasks
Eligible to obtain and maintain an active U.S. Secret security clearance
You are a self starter, outcome driven, and an excellent communicator

Preferred

Experience working with the latest AMD SOC/FPGAs
Knowledge of AMD FPGA NOC and advanced design features (partial reconfiguration, DFX, segmented flow, etc)
Working knowledge of signal processing flows (data converter to bits)
Exposure to wireless communications and/or radar systems design
Experience with RF test equipment (Spec An, Sig Gens, Oscilloscope, etc)
Knowledge or experience using AMD AIE tiles for processing
$166,000—$220,000 USD
The salary range for this role is an estimate based on a wide range of compensation factors, inclusive of base salary only. Actual salary offer may vary based on (but not limited to) work experience, education and/or training, critical skills, and/or business considerations. Highly competitive equity grants are included in the majority of full time offers; and are considered part of Anduril's total compensation package. Additionally, Anduril offers top-tier benefits for full-time employees, including:

Benefits

Vision
Equity/RSU

Company

Anduril Industries

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Source: greenhouse

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