Senior FPGA Verification Engineer

Boulder, Colorado, United Statesfull time

On Site

senior

$165k–$218k

H1B: no

Anduril Industries Senior FPGA Verification Engineer at Anduril Industries designing verification environments and testbenches for FPGA devices. Provide technical leadership and contribute to ASIC/FPGA verification flow improvements.

Responsibilities

Verification environment architecture and design using tools like SystemVerilog or OVM/UVM
Creation of written test plan, testcases, code coverage tracking, and functional coverage tracking
Testbench development for the verification of RTL blocks using VHDL or SystemVerilog
Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA verification flow
Contribute to engineering estimates for new program pursuits.
Provide technical leadership for project verification teams by breaking down work, planning activities, and reporting status

Qualification

A Bachelor's in Electrical EngineeringProven ability to design$165

Required

A Bachelor's in Electrical Engineering, Computer Engineering, or a related technical field is typically required.
8+ years of experience developing HDL firmware for FPGA devices
Demonstrated experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment.
experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment.
Proven ability to design, implement, and execute verification testbenches for RTL blocks using VHDL and/or SystemVerilog.
experience applying chip-level verification methodologies, including constrained-random testing, functional coverage analysis, and assertion-based verification (SystemVerilog)
Experience using revision control systems such as Git or Subversion to manage source code, collaborate across engineering teams, and maintain configuration integrity.
Eligible to obtain and maintain an active U.S. Secret security clearance

Preferred

Experience with ASIC/FPGA lab validation and debug using standard lab equipment, along with familiarity with DFT, manufacturability, and production test concepts.
Proficiency with Unix/Linux environments, scripting or software development (C, C++, Python, Perl, or shell), and industry-standard ASIC/FPGA simulation and synthesis tools such as QuestaSim, Synplify, Quartus, or Vivado.
$165,000—$218,000 USD
The salary range for this role is an estimate based on a wide range of compensation factors, inclusive of base salary only. Actual salary offer may vary based on (but not limited to) work experience, education and/or training, critical skills, and/or business considerations. Highly competitive equity grants are included in the majority of full time offers; and are considered part of Anduril's total compensation package. Additionally, Anduril offers top-tier benefits for full-time employees, including:

Benefits

Vision
Equity/RSU

Company

Anduril Industries

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Source: greenhouse

Active within the past hour

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