Senior Product, Test and Yield Enhancement Engineer - Taiwan

Sunnyvale, CA · Remotefull timeRemote

Apply on Employer Site

senior

H1B: yes

Cerebras Senior Product, Test and Yield Enhancement Engineer at Cerebras leads test strategy and yield improvement for wafer-scale AI processors. The role involves test program development, failure analysis, and collaboration with cross-functional teams in Taiwan.

Responsibilities

Cerebras is seeking a senior VLSI product and test engineer with 10+ years of experience in semiconductor testing, failure analysis and yield enhancement.
Develop and optimize production test programs for wafer-scale AI processors.
Drive high-volume manufacturing testing in partnership with foundries and outsourced semiconductor assembly and test providers (OSATs).
Implement and optimize design-for-test strategies, including scan, built-in self-test (BIST), automatic test-pattern generation (ATPG) and functional testing.
Analyze automated test equipment (ATE), Shmoo, parametric and defect data to improve yield and fault tolerance.
Develop failure-analysis and fault-isolation methods for defective cores, tiles and other functional blocks.
Build efficient wafer-level test flows for massively parallel compute, mesh and network-on-chip architectures, and die-to-die interconnects.
Partner closely with DFT, architecture, design, performance, software and manufacturing teams.
Optimize voltage-frequency operating limits, current, thermal behavior, power delivery and parallel die-testing capabilities.
Support wafer and lot disposition decisions throughout high-volume manufacturing.

Qualification

BS or MS in Electrical EngineeringStrong experience in test developmentExpert-levelExperience specifyingProgramming experience with CKnowledge of wafer-scale packagingLocation and Travel

Required

BS or MS in Electrical Engineering, Computer Engineering or a related field.
10+ years of semiconductor product or test-engineering experience supporting highly integrated devices.
Strong experience in test development, silicon debug, test optimization and yield improvement.
Experience testing large parallel processors, GPUs, CPUs or networking ASICs incorporating SRAM, DDR/DRAM or HBM.
Expert-level, hands-on experience with the Advantest V93000 platform; Teradyne experience is a plus.
Experience specifying, designing, developing and debugging load boards and probe cards for advanced production-test and DFT requirements.
Strong cross-functional collaboration and problem-solving skills.
Experience working with Git-based development and release flows.

Preferred

Programming experience with C, C++, Python or Perl for large-scale test-data analysis.
Experience with semiconductor test and failure-analysis tools or techniques such as Tessent, OBIRCH, IREM and LADA.
Experience testing high-speed SerDes at the ATE, package or system level.
Experience with analog blocks embedded within large digital ASICs.
Experience applying advanced data-analysis or machine-learning techniques to yield optimization.
Knowledge of wafer-scale packaging, TSVs, advanced interconnects, in-line diagnostics and defect-mitigation techniques.
Location and Travel
This position is based in Taiwan and requires at least 50% travel within Taiwan.

Company

Cerebras

View company page

Source: ashby

Active within the past hour

Remote-friendly

More roles at Cerebras

Manufacturing Automation Engineer

Headquarters/Sunnyvale Office

AI Fleet Platform Software Engineer

Sunnyvale, CA · Remote

Senior Counsel, Data Center & Infrastructure

Sunnyvale, CA · Remote

Managing Counsel, Data Center & Infrastructure

Sunnyvale, CA · Remote