Senior Digital Verification Engineer - Contract

Required

• Education: Bachelor's or Master's/PhD in Electrical Engineering, Computer Engineering, or a related field.
• Experience: 8+ years of ASIC/SoC design verification, with multiple projects taken from testbench development through tapeout.
• UVM and SystemVerilog: Expert in UVM testbench architecture and SystemVerilog for verification, including classes, constraints, interfaces, functional coverage, and assertions (SVA).
• Coverage closure: A track record of driving functional and code coverage to sign-off on multi-million-gate designs.
• Debug: Strong ability to debug complex simulation failures independently using industry-standard tools (VCS/Verdi, Xcelium, or Questa).
• Scripting: Python for regression automation, log analysis, and coverage post-processing.
• Independence: Able to ramp quickly on a new design and deliver with minimal supervision.
• Communication: Clear written and verbal communication of status, risks, and tradeoffs to peers and leadership.
• Ways to stand out
• C/C++ for reference modeling or SoC-level tests, including DPI integration.
• Formal verification with JasperGold or similar tools.
• Experience building or using agentic AI flows for DV, such as automated regression triage or failure debug.