Digital Verification Engineer

Austin, TXfull timeOn Site

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mid

$130k–$180k

H1B: no

Efficientcomputer Digital Verification Engineer at Efficientcomputer leads functional verification of complex SoC/IP designs from specification through tapeout. The role owns verification strategy, defines methodology standards, and guides a team of verification engineers.

Responsibilities

Define the end-to-end verification strategy across block, subsystem, and full-chip levels aligned with tapeout milestones
Author and review verification plans mapping specifications to features, stimulus strategies(traditional stimulus generation, compiler driven), coverage goals, and sign-off criteria
Architect scalable UVM-based testbench environments including agents, scoreboards, reference models, and coverage monitors
Drive constrained-random stimulus development targeting protocol interactions, concurrency, error injection, and corner cases
Define and close functional coverage models through systematic hole analysis, targeted tests, seed optimization, and regression tuning
Deploy SystemVerilog Assertions for protocol compliance, interface checks, and design invariants across all simulation runs
Lead full-chip verification including boot sequences, interrupt handling, DMA flows, power-on reset, and multi-block interactions
Ensure CDC, RDC, and multi-power-domain verification in coordination with specialist tools and teams
Debug complex simulation failures spanning multi-block interactions, protocol violations, race conditions, and timing-dependent corner cases
Own the bug lifecycle — triage, prioritization, tracking, fix verification, and cross-functional resolution with RTL designers and architects
Manage the regression framework — defining suites, maintaining stability, optimizing throughput, and integrating with CI/CD pipelines
Coordinate simulation-to-emulation handoff ensuring verification collateral transitions effectively to emulation environments

Qualification

EducationExperienceUVM MasterySystemVerilogCoverage ClosureDebug SkillsSoC ArchitectureScripting & AutomationCommunication

Required

Education: Bachelor's or Master's/PhD degree in Electrical Engineering, Computer Engineering, or a related field.
Experience: 10+ years of progressive experience in ASIC/SoC design verification, with at least 3 years in a lead role owning verification strategy, sign-off, and team execution.
UVM Mastery: Deep expertise in UVM-based testbench architecture and constrained-random verification methodology — not just usage, but architectural decision-making and optimization.
SystemVerilog: Advanced proficiency in SystemVerilog for verification including classes, constraints, functional coverage, assertions (SVA), interfaces, and packages.
Coverage Closure: Demonstrated track record of driving functional and code coverage to tapeout sign-off on complex, multi-million-gate SoC/ASIC designs.
Debug Skills: Proven ability to debug deeply complex simulation failures spanning multiple design blocks, protocols, and abstraction levels.
SoC Architecture: Strong understanding of modern SoC building blocks — processors (ARM, RISC-V), interconnects (AMBA AXI/ACE/CHI), memory controllers, DMA engines, interrupt controllers, and standard peripherals.
Scripting & Automation: Proficiency in Python, Perl, or Tcl for test automation, log analysis, coverage post-processing, and regression flow development.
Communication: Clear and effective communication of verification status, risk, and trade-offs to technical peers and program leadership.