SOC Integration Engineer

Required

• Demonstrate proficiency in SystemVerilog and scripting languages such as Python or Perl to drive chip design RTL and associated flows.
• Possess a proven track record in integrating high-performance computing elements (CPUs, GPUs, accelerators) and high-speed interconnect standards like UCIE, while managing memory and logical functionalities within the SOC RTL.
• Apply working knowledge of logical equivalency verification for SOC-level subsystem interfaces, collaborating with physical design teams to incorporate floorplan requirements into the RTL.
• Manage memory wrapper generation, including the integration of DFT wrappers into Subsystem RTL.
• Provide automation support for generating and configuring SOC RTL with user-defined Subsystems for Design Verification (DV) purposes.
• Leverage hands-on experience with AI-driven tools to architect automation for SOC integration and facilitate technical support for cross-functional implementation teams.
• Utilize hands-on experience with design synthesis, linting, clock & reset-domain-crossing, and timing constraint validation to ensure high-quality SOC sign-off.
• Familiarity with emulation platforms and verification methodologies is highly desirable.