7+ years of Analog Layout Design experience

Understanding of the Semiconductor Fabrication process and device/layout cross-sections

Minimum 3 years of experience with the following TSMC FinFET processes: 2nm, 3nm, 4nm, 5nm

Several tape-outs with FinFET processes, owning major layout macros (ADC, DAC, TIA, CDR, PLL, BGB, LDO)

Expert-level knowledge of block/macro floor-planning, block integration, routing, clock distribution, and power grid implementation

Expert-level knowledge of layout considerations for device matching, symmetry, parasitic reduction, and noise isolation

Expert-level knowledge of running and debugging LVS/ERC/DRC/Density/DFM/Antenna verifications

Expert-level knowledge of EM/IR analysis

Expert-level knowledge of Cadence Virtuoso and Calibre/Pegasus verification tools

Understanding of ESDs and Clamps, and their layout considerations

Understanding of layout effects such as LOD/OSE/PSE/WPE/MBE/LDE

Experience with lane integration and tape out versifications

Senior Analog Layout Designer

Qualification