ASIC Design Intern

San Joseinternship

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$73k

H1B: no

Skhynixmemorysolutionsamericainc ASIC Design Intern at SK hynix Memory Solutions America working on RTL design for IP in high-performance SSD controllers. Collaborate with Design Verification, Silicon Validation, and Firmware teams to ensure design quality.

Responsibilities

RTL design (Verilog/SystemVerilog) for IP based on existing module or new specifications.
Collaborate, create clear documentation and communication with Design Verification, Silicon Validation, and Firmware teams to ensure design quality.

Qualification

EducationAdvanced EducationScripting skills (Python

Required

Education: Currently enrolled in BS/MS/PhD program in Electrical Engineering, Computer Engineering, or related field.
Proficiency in logic design and micro-architecture; RTL coding in Verilog and/or SystemVerilog language.

Preferred

Advanced Education: Master’s or PhD in Electrical Engineering with working experiences.
Experience or coursework in digital logic design, verification methodologies, and protocols (AMBA, PCIe, NAND, DDR)
Scripting skills (Python, Perl, TCL) and Linux command-line experiences
Strong problem-solving and communication skills
Proficiency in AI tool to generate synthesizable and functional RTL code

Company

Skhynixmemorysolutionsamericainc

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Source: greenhouse

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