Research Scientist - Loop Engineering and AI Infrastructure

Preferred

• Hands-on experience with an AI-assisted hardware/software co-design loop framework, such as CHIA, SKHY, or with another agentic or scripted flow.
• Proficiency with Chisel, XLS, or RISC-V SoC integration, and with RTL simulation or FPGA prototyping.
• Experience with commercial ASIC flows, and with reading timing, power, and area reports.
• Experience with architecture simulators.
• Background in memory or storage reliability: device noise, ECC, endurance, or error models.
• Papers or patents in computer architecture, VLSI CAD, or hardware/software co-design.
• What success looks like:
• In the first year, a loop-engineering hire produces a reusable co-design loop for an SoC decision and a written best practice. An AI infrastructure hire produces a result that ties a bottleneck, a memory-device noise effect, or a compute-memory architecture to host-level AI performance. A hire for both produces both.