Sr. Staff / Principal Physical Design Engineer

Preferred

• Experience at 5nm or 3nm process nodes with FinFET and multi-patterning design rules
• Familiarity with low-power design techniques including UPF, clock gating, multi-Vt, and voltage islands
• Strong programming skills in Tcl, Perl, and Python for flow automation and data analysis
• Knowledge of ECO implementation and clock reconstruction (CRPR, useful skew) methodologies
• Experience leading or mentoring a team of physical design engineers on complex SoC projects
• Exposure to memory-centric interfaces and systems such as SSD SoC, HBM, or HBF (High Bandwidth Flash) base die designs (a plus, not required)
• Familiarity with chiplet and die-to-die (D2D) interconnect technologies, including Universal Chiplet Interconnect Express (UCIe) or equivalent D2D PHY protocols (a plus, not required)
• BASE COMPENSATION: $160,000/yr - $220,000/yr