We are hiring a research intern in loop engineering: best practices for closed-loop flows that automate, optimize, and explore SoC designs. These are AI-assisted hardware/software co-design flows. CHIA, from UC Berkeley, is one example of a framework you may use.

Study how a design loop should be structured: which steps belong in it, what feedback each step returns, and how search, verification, and physical-design results drive the next iteration.

Implement the loop with languages and tools such as Chisel and XLS, together with simulation, software build, and physical-design tools.

Apply it to an SoC problem such as microarchitectural exploration, RTL implementation and verification, or power, performance, and area optimization.

Compare loop designs on the quality of the design point, the cost of the search, reproducibility, reuse, and how reliably a failure is diagnosed.

Make the loop reliable enough to rerun: clear interfaces between steps, cached results, regression checks, and reports that support a conclusion.

Progress toward a bachelor’s, master’s, or Ph.D. in electrical engineering, computer engineering, computer science, or a related field.

Coursework or project experience in loop engineering, computer architecture, digital design, VLSI, or electronic design automation.

Fluency in Python, and comfort reading and changing an existing codebase.

Ability to pose a small research question, keep a record of what changed, and explain the result.

Research Intern - Loop Engineering

Responsibilities

Qualification

Required

Preferred

Company

Skhynixmemorysolutionsamericainc

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