Analog Layout Engineer (Lead)

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senior

H1B: no

Kandou AI The Analog Layout Engineer (Lead) at Kandou AI will lead custom layout and verification of analog circuits for high-speed chip-to-chip communication links in advanced semiconductor nodes. The role involves close collaboration with design teams and customer interaction.

Responsibilities

Position in custom layout and verification of analog circuits, cells, blocks, and IP
Layout and verification of very high-speed analog circuits
Interact closely with design team to understand requirements and implement solutions
Support IP and chip level integration
Support and interact with customers on requirements and IP delivery

Qualification

Self-motivatedBackground in Semiconductor PhysicsGraduate in E

Required

Understanding of layout approaches and techniques for high-speed circuits, matching constraints, minimization of parasitics, power grids and ESD requirements
Experience on modern semiconductor process technologies including 28nm, 14/16nm, 7nm
User of EDA tool for design and verification like Cadence Virtuoso, Spectre/HSpice, Calibre/PVS DRC/LVS, parasitics extraction and modelling, EM, and IR drop, ESD, etc.
Self-motivated, with strong sense of ownership and responsibility. Good communicator and team player
Manage workload and schedules and report to internal management team
Background in Semiconductor Physics
Graduate in E.E.