Intern, Power-Thermal Simulation Software Engineer

SSI San Jose internship

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H1B: yes

Samsung Semiconductor Software engineering intern role at Samsung Semiconductor focused on developing power and thermal simulation tools for AI memory systems. Responsibilities include building automation pipelines and implementing trace-driven power-thermal simulation engines.

Responsibilities

Samsung’s Power & Thermal Lab is seeking a software engineering intern to contribute in the development of our power and thermal simulation tool.
We are a small, fast‐moving team where direct ownership and minimal busywork empower every member to tackle the same real‐world problems. Working with authentic data, real partners, and production‐grade results, our contributions flow straight into platforms used across the company.
As an intern, you will support research and product teams across multiple projects, including providing end‐to‐end simulation, regression testing, and data‐pipeline management. You will work on real projects with tangible results, receive mentorship, and help shape the scope of work in a collaborative environment where hardware, software, and thermal experts work side‐by‐side on next‐generation AI memory technologies.
Location: Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work policy
Reports to: SVP, R&D (Power & Thermal Lab)
Build automation pipelines for simulation runs, regression testing, and result tracking.
Implement and optimize a trace‐driven power‐thermal simulation engines.
Generate transient power maps, perform spatiotemporal hotspot analysis, and interface with reduced‐order/CFD‐calibrated thermal solvers.
Develop high-fidelity, advanced RTL- SystemC-, and C-based power macromodels for AI memory component IPs using analytical modeling, LUT, FSM, NN, and their hybrid.
Extract activity-, value-, and state-dependent power features from C/SystemC/RTL simulations.
Define power-relevant functional states (transaction/state-based abstraction).
Calibrate models using synthesis‐assisted anchors and validate against RTL/gate‐level and silicon data.