Astera Labs Sr. Principal Systems / Rack SW Architect at Astera Labs responsible for defining architecture for next-generation AI infrastructure. Drive innovation across silicon integration, platform firmware, and rack-scale system design.
Responsibilities
AI Platform & Rack-Scale Architecture
Define the end-to-end architecture for AI platforms, from node-level design to rack-scale composable systems
Drive adoption of PCIe / UAlink -based fabrics for disaggregated compute, memory, and accelerator scalability
Architect solutions for GPU/accelerator-dense systems optimized for AI training and inference workloads
Lead integration of connectivity solutions — retimers, switches, and fabric controllers — aligned with Astera Labs' product ecosystem
System Architecture & Platform Leadership
Lead system architecture and design for high- performance compute platforms optimized for AI and accelerator-driven workloads
Design and integrate PCIe-based subsystems including GPU, accelerator, and high-speed I/O components leveraging PCIe Gen5/6 technologies
Define and implement GPU-enabled server platforms for AI training, inference, and HPC workloads
Architect and optimize high-speed Ethernet networking interfaces (25G/100G/400G+) within platform designs
Define the technical vision and multi-year Product roadmap for AI infrastructure platforms
Drive the software end-to-end architecture for ASTERA LABS's rack-scale products
Qualification
Bachelor's degree in Computer ScienceDeep expertise in server BIOS/UEFIExperience with CPUBackground in AI training clusters
Required
Bachelor's degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field
20+ years of experience in system architecture, server firmware, or platform engineering
Deep experience in designing architecture for scalable and performant server systems, particularly at the SW/HW interface.
Strong understanding of networking technology & protocols (e.g. Ethernet, Infiniband)
Previous experience working with complex system software for accelerators such as GPUs, DPUs, or FPGAs
Expertise in out-of-band and in-band management architectures.
Knowledge of system management protocols such as Redfish and IPMI.
Experience working with platform security experts to define tradeoffs between security and ease of use.
Demonstrable experience in implementing left shift strategy to de-risk program execution. Excellent written and verbal communication skills.
Deep expertise in server BIOS/UEFI, OpenBMC and BMC firmware stacks, and Redfish or datacenter management frameworks
Strong knowledge of PCIe architecture and performance optimization (Gen4/5/6)
Experience with CPU, memory, and system-level performance tuning for high-performance computing or AI platforms
Preferred
Master's degree or PhD in Computer Science, Electrical Engineering, or a related field
Experience with rack-scale composable infrastructure and disaggregated architectures
Background in AI training clusters, accelerator-based systems, or hyperscale datacenter design
Expertise in high-speed interconnect solutions such as retimers, switches, and fabric ICs
Experience with platform lifecycle management systems and fleet-level automation
Contributions to industry standards bodies or open-source firmware ecosystems
Demonstrated ability to define multi-year technical roadmaps and influence executive strategy
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.