Distinguished Engineer, SerDes Clocking at Upscale AI · LumiJobs

Responsibilities

We are building a world-class SerDes engineering organization to enable next-generation, ultra-high-speed connectivity for AI data centers and high-performance computing.
We are seeking an exceptional technical leader to define the clocking architecture for next-generation SerDes, spanning ultra-low-jitter phase-locked loops (PLLs) and high-performance clock distribution networks.
This is a senior individual contributor role for a recognized expert in high-speed clocking technology who can drive architectural innovation, lead critical circuit development, and solve some of the most challenging jitter, coupling, and power-efficiency problems in advanced CMOS.
Clocking Architecture: Define and drive the end-to-end clocking architecture for next-generation SerDes, including PLLs, clock generation, multiphase clocking, clock distribution, and integration with transmitter and receiver subsystems.
Ultra-Low-Jitter PLL Design: Lead the architecture and development of ultra-low-jitter PLLs targeting less than 100 fs RMS integrated jitter in advanced CMOS technologies at 5nm and below, meeting stringent system-level timing and noise requirements.
PLL Architecture Innovation: Evaluate and develop hybrid, digital, and other advanced PLL architectures, making informed trade-offs among jitter, power, area, tuning range, robustness, and implementation complexity.
Multi-PLL Coupling Management: Develop architectural and circuit-level solutions to mitigate coupling among multiple PLLs and clock-generation blocks, including supply coupling, substrate noise, electromagnetic interactions, reference spurs, and clock-to-clock interference.
Power-Efficient Clock Distribution: Define and implement advanced clock distribution architectures, including resonant clocking techniques, to reduce clocking power while maintaining stringent jitter, skew, phase-noise, and timing requirements.
EM Analysis and Optimization: Use electromagnetic simulation and extraction tools to analyze and optimize inductors, resonant networks, clock distribution structures, coupling paths, and high-frequency interconnects.
Modeling and Verification: Develop SystemVerilog-based behavioral models, verification environments, and architectural models for PLLs and clocking subsystems to enable early system integration, design exploration, and verification of key performance requirements.
Cross-Functional Technical Leadership: Partner with SerDes TX, RX, ADC, digital, AMS layout, package, and silicon validation teams to optimize overall link performance and ensure clocking architecture decisions align with system requirements.
Silicon Execution and Correlation: Drive design reviews, implementation strategy, silicon characterization, jitter and phase-noise analysis, and simulation-to-silicon correlation.

Distinguished Engineer, SerDes Clocking

Responsibilities

Qualification

Required

Company

Upscale AI

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