The SRAM Lab is seeking an intern to support the development, simulation, and optimization of SRAM circuits.

Our lab designs, develops, and optimizes advanced SRAM circuits for next‐generation semiconductor products. We integrate rigorous circuit analysis with innovative layout strategies to deliver memory solutions that satisfy the stringent power, performance, and area (PPA) requirements of future AI and mobile ecosystems.

As an intern, you will contribute to our full‐stack SRAM projects—covering architecture, schematic design, and silicon‐level verification—while researching novel architectures that boost computing‐platform efficiency and ensure seamless SoC compatibility.

Location: Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work policy

Reports to: Sr. Director, SRAM Design

Assist in the design and simulation of SRAM circuits using industry-standard EDA tools

Perform transistor-level schematic design for SRAM bitcell, sense amplifiers and peripheral circuits

Conduct simulations to verify functionality, timing, power and reliability of SRAM design

Document design processes, simulation results, and findings in technical reports or presentations

Complete other responsibilities as assigned.

Pursuing Masters, or PhD in Electrical or Electronic Engineering preferred

Must have at least 1 academic quarter/semester remaining

Intern, SRAM Design Engineer

Responsibilities

Qualification

Required

Preferred

Benefits

Company

Samsung Semiconductor

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