Responsibilities

As a Senior member of the Mesh & Opportunistic Networking team, you will own the FPGA realization of the digital signal processing that powers our software-defined radio. You will take wireless communication algorithms from concept through behavioral modeling in MATLAB/Simulink, into synthesizable RTL, and onto silicon — meeting aggressive timing, resource, and power targets on a Zynq UltraScale+ MPSoC. You will apply deep expertise in DSP, digital communications, and FPGA design to deliver a robust, high-performance OFDM modem, and you will collaborate closely with firmware, systems, RF, and product engineering to bring the full radio together. You will mentor junior engineers, raise the technical bar for our model-based design and verification practices, and continue to grow your own technical leadership. Join a passionate engineering team dedicated to overcoming complex challenges, and help deliver technologies that positively impact Law Enforcement, Public Safety, and their surrounding communities.
Location - This role is based out of our Boston or Scottsdale offices and follows a hybrid schedule. We rely on in-person collaboration and ask that team members work onsite Tuesdays through Fridays, with the flexibility to work remotely on Mondays, unless there is an approved workplace accommodation. We believe that connection fuels innovation, and our in-office culture is designed to foster meaningful teamwork, mentorship, and shared success.
Research, model, and implement industry-leading SDR and digital communications algorithms — OFDM modulation/demodulation, FFT/IFFT, channel estimation and equalization, synchronization, MIMO, and forward error correction (LDPC) — for products in our mesh and connected-device portfolio
Develop floating- and fixed-point behavioral reference models in MATLAB/Simulink, make quantization and architecture trade-offs, and validate algorithm performance against link-budget and BER/PER requirements
Generate and integrate RTL from Simulink using HDL Coder, and author hand-written VHDL/Verilog where custom or performance-critical logic is required
Implement designs in Vivado through the full flow — synthesis, place-and-route, and timing closure — authoring and refining XDC timing and physical constraints to meet timing on high-utilization, multi-clock designs
Architect and implement on-chip interfaces and data movement: AXI4 / AXI4-Stream, DMA, register interfaces, FIFOs, and robust clock-domain-crossing (CDC) logic
Build and maintain rigorous verification: Simulink/HDL co-simulation, bit-true comparison against the reference model, RTL testbenches, and automated regression suites
Integrate the modem with the RF transceiver front end (e.g., ADRV9001) and with the ARM application cores, partitioning functionality across the heterogeneous SoC
Collaborate with electrical engineering on concerns that span the FPGA/RF boundary — power and thermal budgets, generation of test and characterization waveforms, and digital pre-distortion (DPD) for power amplifier linearization
Bring up, characterize, and debug the radio on hardware using oscilloscopes, logic/protocol analyzers, spectrum and vector signal analyzers, and on-chip debug (ILA/VIO)
Collaborate with firmware engineering to define and debug the hardware/software interface, register maps, and data pipelines

Senior FPGA & Firmware Engineer - SDR at Axon · LumiJobs

Senior FPGA & Firmware Engineer - SDR

Responsibilities

Qualification

Preferred

Benefits

Company

Axon

More roles at Axon