Quadric Senior Hardware Engineer at Quadric contributes to processor architecture and microarchitecture design, including RTL implementation and PPA optimization. The role involves timing closure and full product cycle involvement.
Responsibilities
This is a rare opportunity to get in on the ground floor of a revolutionary new processor architecture. As a senior member of our chip design team, you will contribute to all stages of the processor design cycle.
Our preference is for a candidate located in the California Bay Area who can regularly collaborate from our Burlingame office.
From time to time, the team and company gather for onsite meetings and offsite events. These in-person moments are an important part of how we build relationships, collaborate effectively, and align on priorities, and participation is expected for all team members.
Contribute to the definition of the processor architecture by understanding its applications
Own microarchitecture definition & RTL implementation of the processor in SystemC or SystemVerilog
Own Power, Performance & Area (PPA) optimization
Contribute to timing closure through full product cycle (front end, back-end, tapeout)
What Success Looks Like
Within your first 6–12 months, you'll:
Independently own a major design block and improve PPA
Develop an in-depth understanding of the architecture and SW interfaces and be able to debug issues across the full SW/HW stack
Package design for customer releases and incorporate customer feedback
Qualification
BS/MS or PhProficiency in SystemCKnowledge of VCS & Verilog/C Co-SimExperience in FPGA design is a plusExperience marketing semiconductor IP
Required
BS/MS or Ph.D. in Electrical or Computer Engineering with a minimum of five years of CPU/GPU/ASIC front-end design
Proficiency in SystemC, SystemVerilog, or Verilog
Strong background in computer architecture
Knowledge of design techniques for low power digital design
Knowledge of VCS & Verilog/C Co-Sim
Experience in data-parallel hardware design for high-performance computing
Experience in FPGA design is a plus
Experience in logic synthesis and performance modeling
Preferred
Experience marketing semiconductor IP, AI accelerators, SoCs, EDA tools, or developer platforms.
Familiarity with automotive safety (ASIL) standards
