Quadric RTL Intern at Quadric supports SoC subsystem development and PPA optimization for the GPNPU platform. The role involves working closely with architects and designers on front-end design and integration.
Responsibilities
This is a chance to get hands-on experience building a next-generation SoC architecture from the ground floor, working directly alongside our hardware team as we bring supercomputer technology to the Edge.
You'll support the SoC design team with subsystem development, third-party IP integration, and PPA (power, performance, area) optimization for Quadric's GPNPU platform — gaining exposure to real front-end design and integration methodologies, and working closely with the architects who define the chip.
Note: Our preference is for this internship to be based out of our Burlingame, California office. Candidates should be based in the Bay Area or able to relocate for the internship period and available to work on site.
Support SoC Subsystem Development
Help design and integrate SoC-level subsystems, working alongside engineers integrating third-party IP (such as NoC, PCIe/UCIe interfaces, DDR, Security, etc.).
Contribute to documentation of SoC architecture and application requirements.
Support PPA Optimization
Assist in analyzing and optimizing Power, Performance, and Area (PPA) at the SoC level.
Get exposure to low-power digital design techniques and timing closure work across front-end stages.
Collaborate Across the Team
Work closely with SoC architects and designers to understand design intent and integration requirements.
Communicate findings, blockers, and technical questions clearly to the team.
Qualification
Currently pursuing a Bachelor'sProficient in SystemVerilog or VerilogExposure to logic synthesis
Required
Currently pursuing a Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a related field.
Familiarity with SoC/ASIC front-end design concepts.
Proficient in SystemVerilog or Verilog.
Prepared to collaborate with architects and designers on subsystem development and integration tasks.
Demonstrated capability in problem-solving, debugging, and clear technical communication.
Preferred
Coursework or project experience with computer architecture, low-power design, or RTL design.
Exposure to logic synthesis, FPGA design, or performance modeling.
Adept with scripting languages like Python and using LLMs to get things done
