CPU Custom Memory Design - SRAMs and Register Files

Required

• Hold a BS or MS degree with 8+ years of experience in custom memory circuit design : SRAMs, and/or Register files.
• Hands-on transistor-level circuit design experience with combo cells, sequential logic in static/dynamic logic families, as well as memory arrays — bit cells, sense amps, decoders — in advanced CMOS nodes.
• Deep knowledge of SPICE simulations, SRAMs / Register File circuit margins, and special memory cell architectures.
• Proficient with industry-standard EDA tools for schematic, layout, extraction, and characterization, applied to custom memory design workflows.
• Demonstrated track record delivering production-level custom memory IP through tape-out, with silicon-validated PPA in high-volume products.
• Deep understanding of end-to-end signoff for custom memories — DRC/LVS/antenna, extraction, SPICE margins, STA, EM/IR — and characterization flows spanning timing, power, and noise.
• Well-versed in STA and Liberty/CCS lib model development and correlation, including timing and power characterization for both Functional and DFT (Design for Test) modes.
• Strong communication and collaboration skills, comfortable working directly with foundry, CAD, and physical design partner teams.
• Substantial experience across the full embedded memory design flow — architecture, circuit design, physical implementation, compiler automation, characterization, and timing/model generation.
• Experience designing and optimizing complex memory sub-blocks (self timed design tracking loops, read/write assist schemes, power-gating headers) and translating PDK device characteristics into cell/bit-cell circuit decisions.
• Proven PPA-focused execution, including SRAM architecture trade-offs, critical-path modeling, full-cut analysis, and extensive Monte Carlo variation studies.
• Demonstrated experience converging on macro verification, including functional formal equivalence (LEC) and dynamic SPICE-versus-RTL co-simulation (cosim) methods.