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Rosaic LabsPosted Sep 29, 2026
CPU RTL Microarchitecture/Design Engineer - Full Time
Santa Clara, CAfull timeOn Site$125k–$250kH1B: no
Rosaic Labs CPU RTL Microarchitecture/Design Engineer to design and implement CPU functional blocks and develop RTL using SystemVerilog/Verilog. Analyze performance tradeoffs and collaborate with verification and physical design engineers.
Responsibilities
- Design and implement CPU functional blocks based on microarchitecture specifications
- Develop, debug, and optimize RTL using SystemVerilog/Verilog
- Analyze performance, timing, area, and power tradeoffs and propose improvements
- Work with verification engineers to develop test plans and achieve functional coverage
- Partner with physical design engineers on area, timing, and power goals
- Participate in microarchitecture and RTL design reviews and write technical documentation
Qualification
Electrical EngineeringComputer EngineeringComputer ScienceA related fieldOut-of-order executionCPU front-end / control logicLoad/store and memory systemsCache hierarchy and coherencyVirtual memoryFloating-point / computer arithmetic
Required
- Bachelor's or Master's degree (or near-term graduation) in one of:
- Electrical Engineering
Company
Rosaic Labs
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