Sr. IC Package Design Engineer (Silicon Engineering)

Austin, TXfull timeOn Site

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senior

H1B: no

SpaceX Sr. IC Package Design Engineer at SpaceX responsible for leading packaging design for custom ASICs and RFICs used in Starlink satellite and ground infrastructure. The role includes package selection, layout, optimization, and cross-functional coordination.

Responsibilities

Own and drive advanced package selection, new product BGA configuration and package structure
Responsible for package/SIP layout, optimization, design verification and tapeout
Interface and coordinate with cross-functional groups throughout SpaceX on new product package selection, feasibility analysis and design
Work cross-functionally, understand trade-offs, constraints, and optimizing silicon floor plan, bump and package pin out
Simulate and optimize signal/power integrity and RF performance of the package design
Drive methodology, innovations, and productivity improvements in package design

Qualification

Substrate design experience for RF

Required

Bachelor's degree in electrical engineering, computer engineering, or physics
5+ years of experience with IC package design

Preferred

Experience with Co-packaged Optics (CPO)
Thorough understanding of signal and power integrity fundamentals
Substrate design experience for RF, digital, high-speed and mixed signal die
Experience with Cadence APD+/SIP or similar design tools
Experience in package design electrical review, SI/PI analysis
Fluent in SI/PI and EM simulation tools such as SIWave, HFSS, ADS
Experience in package design for manufacturing reviews
Familiar with BGA package substrate technologies

Company

SpaceX

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Source: greenhouse

Active within the past hour

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Must-Have Skills for This Role

IC package designBGA configurationCadence APD+/SIPSIWaveHFSSADS

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