Develop the verification infrastructure and automation environment involved in build, simulation, regression and triages.

Lead the verification for IP blocks of an AI accelerator by working with architects and RTL engineers.

Create direct or random testbench, define verification scope and test plans for both functional and performance validation, close the verification quality metrics.

Provide comprehensive documentation of verification strategy and ensure test environment is easy to use.

Mentor junior engineers when necessary

Work cross-functionally in debugging failures with design, compiler and simulation engineers

Bachelor’s with 5+ years, or Master’s with 3+ years, or PhD's with 0+ years of industry experience.

Strong background in SoC or IP verification and test bench development using UVM, System Verilog, C/C++ and scripting languages such as Perl/Python.

Experience verifying at multiple levels of logic from scratch, starting from complex IP blocks to dies to SoCs to full system testing

Understanding RTL and strong overall debugging skills

Prior experience with computational logic, interconnect networks and/or memory system is desirable

Strong background in microarchitecture and computer architecture preferably in the area of AI accelerators

Senior Engineer, Design Verification

Responsibilities

Benefits

Company

Samsung Semiconductor

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