Distinguished Formal Verification

San Josefull time

On Site

senior

$230k–$285k

H1B: yes

Astera Labs Distinguished Formal Verification Engineer at Astera Labs leads formal verification strategy and methodology development for next-generation connectivity products. Acts as technical authority and mentors global engineering teams.

Responsibilities

Strategic Leadership & Methodology Development
Define and evolve formal verification strategy, methodologies, and best practices across all product lines for PCIe, CXL, Ethernet, UCIe, and UALink protocols
Serve as technical authority on formal verification, providing expert guidance to engineering leadership on risk mitigation and design quality
Represent Astera Labs in industry forums, standards bodies, and technical conferences as a thought leader in formal verification
Drive cross-functional collaboration to influence technical direction across the organization
Technical Execution & Innovation
Develop detailed formal verification test plans based on design specifications and collaborate with design teams to refine micro-architecture specifications
Identify key logic components and critical micro-architectural properties essential for ensuring design correctness
Implement formal verification models, abstractions, assertions, and utilize assertion-based model checking to detect corner-case bugs
Apply complexity reduction techniques using industry-standard EDA tools to achieve proof convergence or sufficient depth
Develop and maintain scripts to enhance FV productivity and streamline verification processes
Team Development & Cross-Functional Partnership

Qualification

Entrepreneurial mindset with proactiveTrack record of recruiting

Required

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field
15+ years of experience in formal verification or 18+ years of experience in traditional design verification with significant formal verification specialization
Strong proficiency in SystemVerilog/Verilog with deep understanding of hardware design verification
Advanced scripting abilities with Python or Perl for automation and productivity enhancement
Proven ability to manage and prioritize multiple high-impact tasks in a dynamic, fast-paced environment with minimal supervision
Strong cross-functional collaboration skills with demonstrated ability to influence technical direction and drive consensus
Entrepreneurial mindset with proactive, customer-focused attitude and ability to think and act quickly while maintaining high quality standards

Preferred

Master's or PhD in Electrical Engineering, Computer Engineering, Computer Science, or Mathematics with focus on formal methods or verification
Hands-on experience with formal verification tools such as Synopsys VCFormal and Cadence JasperGold
Experience with both bug hunting and static proof verification techniques
Familiarity with automating formal verification workflows within a CI/CD environment
Deep knowledge of high-speed serial protocols: PCIe Gen 4/5/6/7, CXL, Ethernet (100G/400G/800G), UCIe, UALink
Participation in industry standards bodies (PCI-SIG, CXL Consortium, IEEE, UCIe Consortium)
Patents or publications in formal verification or hardware verification methodologies
Track record of recruiting, mentoring, and developing formal verification talent across distributed teams

Company

Astera Labs

View company page

Source: greenhouse

Active within the past hour

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