Principal Digital Design Engineer (AI Fabric)

San Josefull time

On Site

senior

H1B: yes

Astera Labs Principal Digital Design Engineer at Astera Labs to architect and implement next-generation digital designs for high-performance connectivity solutions. Own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, PD and DFT teams.

Responsibilities

Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving digital design.
Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues.
Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance.
Work closely with post-silicon teams to facilitate silicon bring-up and debug.
Mentor junior engineers to develop their technical skills and expertise.
Actively contribute to the development and improvement of silicon development processes.
Drive designs to production, ensuring accountability for quality, schedule, and overall design success.

Qualification

Education & ExperienceDigital Design ExpertiseRTL codingDesign for test (DFT) implementationProtocols & IntegrationThe base salary range is $185

Required

Education & Experience:
Bachelor’s degree in electrical engineering or equivalent.
8+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets
Digital Design Expertise:
Architecture definition and micro-architecture development
RTL coding, functional simulation, and synthesis
Timing closure and gate-level simulation (GLS)
Design for test (DFT) implementation
Production experience with advanced CMOS nodes (≤7nm)
Protocols & Integration:
Deep expertise in at least one high-speed protocol—PCIe , Ethernet, Infiniband, DDR, or similar
Third-party IP integration and verification.

Preferred

Track record of delivering multiple high-performance designs to production in data-center environments
Hands-on collaboration with embedded firmware teams; deep understanding of firmware development challenges and constraints
Familiarity with standard embedded processor subsystems (RISC-V, Arm, etc.)
Proven contributions to design methodology, CAD automation, or design infrastructure to improve productivity or design quality
The base salary range is $185,000.00 USD – $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Company

Astera Labs

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Source: greenhouse

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