Develop RTL (Verilog/SystemVerilog) for the IO die, integrating UCIe, PCIe, and other high-speed interconnect IP into a cohesive chiplet-based architecture.

Integrate internal and third-party interconnect IP — UCIe, PCIe, CXL, die-to-die, and NoC — into the IO die, including configuration, glue logic, clock/reset, and interface bridging.

Modify and customize PCIe and other interconnect IP as needed — controller, PIPE/PHY interface, and configuration logic — to meet die-level requirements and close functional gaps.

Define and implement die-to-die and chiplet interfaces using UCIe, ensuring protocol compliance and interoperability across chiplets.

Own the microarchitecture and RTL for IO subsystems such as PCIe/CXL controllers, UCIe adapters, and interconnect fabric bridges.

Collaborate with verification engineers to develop test plans and debug functional issues at the IP, subsystem, and die level.

Work with architecture, PHY/SerDes, physical design, and software teams to close requirements across performance, power, area, and interoperability.

Make design decisions out of a large design trade-off space across performance, power, latency, bandwidth, and cost.

Develop and automate IP integration and RTL assembly flows using scripting and agentic AI tools and frameworks to improve turnaround time and quality of results.

Communicate effectively with stakeholders, including users, partners, and management, to ensure that the die is delivered on time and within budget.

Complete other responsibilities as assigned.

Bachelor’s with 5+ years, or Master’s with 3+ years, or PhD's with 0+ years of industry experience.

Senior RTL Engineer, IO Die and Interconnect IP

Responsibilities

Benefits

Company

Samsung Semiconductor

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