SI/PI analysis of designs and optimization within 2D/2.5D/3D packages

Close interaction with Package Layout Designers, ASIC PD and IP teams as well as Board Schematic/Layout/SI/PI teams to optimize the best electrical performance

Drive SI requirements into interposer/substrate layout (high-speed routing: 112G/224G) from preliminary design through tape-out.

Drive PDN design and decoupling strategy across substrate and interposer, owning DC IR drop, dynamic IR drop, and impedance targets across all rails.

Own ball map / C4 / BGA pin assignment from soft freeze through final freeze in partnership with package layout, ASIC PD, and board layout teams.

Support board-level SI/PI and rack-level scale-up topology studies, including rack test vehicle design and cable characterization.

Participating in cross-functional meetings and design reviews.

You may be a good fit if you have (Must-have qualifications)

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field with a strong understanding of signal integrity and power integrity concepts and fundamentals.

8+ years of SI/PI experience on high-performance ASIC, processor, or accelerator platforms.

Proven experience defining and closing PDN for high-power silicon, including substrate and PCB plane design, decap strategy, and dynamic IR/EM analysis.

Experience with developing systems with high-speed interfaces like HBM, SerDes and D2D interfaces.

Advanced Packaging SI/PI Engineer

Responsibilities

Qualification

Required

Benefits

Company

Etched

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